The present invention relates to signal processing used in field of electronics, and more particularly, to a method and system for fine tuning a sampling clock of analog signals having digital information for optimal digital display. The method and system are based on fine tuning frequency and phase of a sampling clock of the analog signals, for sampling incoming analog signals having digital information within an optimal sampling period, thereby enabling optimal display by a digital display device.
Currently, most common methods and systems of transmitting computer display information to display devices are based on using analog transmission. For example, the VGA format was originally defined by VESA (Video Electronics Standards Association) and other organizations for the purpose of providing a universal format for transmitting analog signals carrying digital pixel information, from a transmitter, such as a PC (personal computer) graphics card, to an analog display device, as described in “Monitor Timing Specifications, VESA and Industry Standards and Guidelines for Computer Display Monitor Timing, Version 1.0, Revision 0.8, Adoption Date: Sep. 17, 1998”, Milpitas, Calif., USA.
FIG. 1 is a block diagram illustrating such an exemplary VGA interface of a transmitter 10 in a typical computer, used in the transmission of analog signals having digital pixel information to a receiver of a display device 12. Image information stored in a frame buffer is transmitted to the receiver of display device 12, by converting digital pixel information stored in the frame buffer to analog pixel information transmitted to the receiver of display device 12 using a digital to analog converter (DAC). In current VGA formats, analog pixel information is transmitted from transmitter 10 to the receiver of display device 12 along three high speed analog transmission lines, marked R (red), G (green) and B (blue), which are the three basic color components of an image.
In addition to analog pixel information, digital synchronization information, known in the art by the terms ‘vertical sync’ and ‘horizontal sync’, and indicated in FIG. 1 by the terms ‘Vsync’ and ‘Hsync’, is sent out to mark the beginning of each frame, and the beginning of each display line, respectively. Vsync and Hsync are sent along two separate lines (as shown in FIG. 1), composite to a single line, or embedded within the green color component of the analog signal. A transmitter timing clock, referred to in FIG. 1 as ‘Tx clock’, provides a timing signal featuring a frequency or rate at which digital pixel information is transmitted from transmitter 10 to the receiver of display device 12 by an analog signal. Digital pixel information transmitted along the R, G, and B, analog transmission lines, and the digital synchronization information signals, Hsync and Vsync, are all synchronized to the transmitter timing clock (Tx clock).
Several standard organizations, such as VESA, have defined many different types of display formats and/or standards. Each display format or standard provides the number of active (displayed) pixels and active (displayed) lines, as well as polarity of Vsync and Hsync, pulse width, cycle time, and position of the active displayed information relative to Vsync and Hsync synchronization pulses. Each display format also defines the frequency or rate of the above described transmitter timing clock (Tx clock), as the frequency or rate at which the digital pixel values are read from the frame buffer, converted to analog signal by the three DACs, and subsequently forwarded to the receiver of the display device. The VGA display interface format was originally defined for analog displays, where each one of the three electronic beam guns within the display device is controlled by the associated analog signal forwarded by the VGA interface.
There is currently a transition from using analog display devices to using digital display devices. Due to the existence of extensive and widespread electronic infrastructure, ordinarily, digital display devices are designed and manufactured for operating with the above described digital to analog VGA interface, but their pixel elements need to be fully defined and individually addressed within the digital display device. For example, in an LCD (liquid crystal display) monitor each pixel is an active element controlling light transmission. In a plasma display monitor each pixel element is a light generator. The luminance information for each color component of each pixel is extracted from the same digital to analog VGA interface, by way of analog to digital conversion, such as by using an analog to digital converter device. This extraction method is a very challenging task because it requires automatic detection of the transmission format and reconstruction of the transmitter timing clock (Tx clock), at the digital display device from the incoming analog RGB signals, and the Hsync and Vsync digital synchronization information signal pulses.
FIG. 2 is a close-up view of an exemplary transmitted analog signal 15 having digital information of a single pixel as part of a transmission format of an analog signal, illustrating pixel timing parameters at a receiver of a digital display device. It is well known that during reception of the analog signals featuring pixels having an R, G, or B, component, at a receiver, such as a receiver of a digital display device, the time period of each pixel is composed of a transition time period 20 during which signal level transition occurs, and a stable time period 22 during which pixel sampling occurs. The signal receiver of the digital display device needs to generate, known in the art as reconstruct, parameters of a sampling clock, using a phase locked loop (PLL) mechanism (functioning with hardware and/or software components) locked to the leading edge of Hsync, or, depending upon the particular type of display format or standard, locked to the trailing edge of Hsync. Frequency of the sampling clock usually exhibits an extent or degree of instability, known as ‘jitter’, shown in FIG. 2 as reconstructed clock phase locked loop (PLL) jitter time periods 28 and 29, which causes the optimal sampling time period 24 to be shorter than the stable time period 22. Sampling analog signals during the reconstructed clock phase locked loop (PLL) jitter time periods 28 and 29, results in less than optimal analog to digital conversion, and subsequently, results in less than optimal display by the digital display device.
There is thus a need for, and it would be highly advantageous to have a method and system for fine tuning a sampling clock of analog signals having digital information for optimal digital display. Moreover, there is a need for such an invention which is readily commercially applicable to essentially any type of electronic system where transmitted analog signals are destined for display by a digital display device.